In integrated circuit production, current wafer test procedures can be divided into two general classes of operation. These are 100 percent wafer testing and wafer sample testing. Prior to the use of wafer sampling methods, the problem of traversing a 100 percent probed wafer in a reasonable travel cycle was resolved in the straightforward manner of applying a serpentine raster sequence. This serpentine raster sequence is also applied to circuit cell samples of the semiconductor wafer in wafer sample testing. Each of these approaches is typically applied in production testing along the shorter dimension of the semiconductor wafer to reduce the total travel of the test probe. In terms of overall travel, this procedure produces a fairly well planned route with only one edge of the tour in discontinuity, which is the reset path of returning to the starting die location. Although present test approaches provide acceptable results, improvements and greater flexibility in wafer testing would prove beneficial in the art.